Flash memories have been widely used in personal computers and electronic devices as non-volatile memories because they can perform data reading, writing and erasing multiple times; and the data saved in the flash memories will not disappear when the power is off.
A typical flash memory unit includes a floating gate made of doped poly silicon and a control gate. The floating gate and the control gate are insulated by a control gate dielectric layer; and the floating gate and the substrate are insulated by a floating gate dielectric layer. When the flash memory unit performs data writing and erasing, electrons are infused into, or pulled out from the floating gate by controlling the voltages applied on the control gate, the source, the drain and the erasing gate. When the flash memory performs a data reading, a working voltage is applied on the control gate, the on/off status of the channel region under the bottom of the control gate is controlled by the energized state of the floating gate, the data saved in the corresponding flash memory unit may be obtained by measuring the current in the channel region.
However, when the flash memory unit performs a data erasing, it is not easy to control the amount of electrons pulled out from the floating gate, excessive electrons may be pulled out from the floating gate; and the floating gate may be positively charged. Therefore, an over-erasing may happen. When the over-erasing is significantly severe, the channel region under the bottom of the floating gate may be on a conducting state without a working voltage, thus a data misreading may happen.
In order to solve the over-erasing problem of the flash memory unit, a select gate is formed at one side of the control gate and the floating gate to form a separated gate structure. FIG. 1 illustrates an existing flash memory unit having the separated gate structure.
As shown in FIG. 1, the flash memory unit includes a substrate 10; a floating gate oxide layer 11 formed on the surface of the substrate 10; a floating gate 12 formed on the surface of the floating gate oxide layer 11; a control gate oxide layer 13 formed on the surface of the floating gate 12; and a control gate 14 formed on the surface of the control gate oxide layer 13. The flash memory unit also includes sidewall spacers 20 covering side surfaces of the floating gate oxide layer 11, the floating gate 12, the control gate oxide layer 13 and the control gate 14. Further, the flash memory unit includes a select gate oxide layer 15 formed on the surface of the substrate 10 at one side of the floating gate 12 and a select gate 16 formed on the surface of the select gate oxide layer 15. The select gate 16 includes a first select gate 17 and a second select gate 18. The sidewall spacers 20 also cover side surfaces of the select gate oxide layer 15 and the select gate 16. Further, the flash memory unit also includes a shared source/drain region 21 formed in the exposed portion of the substrate 10 between the select gate 16 and the floating gate 12, a source region 22 formed in the exposed substrate 10 at the other side of the select gate 16; and a drain region 23 formed in the exposed portion of the substrate 10 at the other side of the floating gate 12. When the over-erasing phenomena is significantly severe, the channel region under the bottom of the floating gate 12 may be on an “on” state even there is no voltage is applied on the control gate 14. However, the channel region under the bottom of the select gate 16 may keep an “off” state, the source region 22 and the drain region 23 may not be turned on, thus the misreading problem may be prevented.
However, the performance of the flash memory unit may not be stable, thus it may be unable to effectively solve the misreading problem of the flash memory unit caused by the over-erasing. The disclosed device structures and methods are directed to solve the problems set forth above and other problems.